4.1 Execution Unit, Bus Interface Unit, and Fetch Queue
Chapter 3 built combinational and sequential circuits. The Intel 8086 connects those ideas into a complete 16-bit microprocessor: combinational circuits calculate and decode, registers preserve state, and a clock coordinates changes.
This section starts with organization rather than instructions. You will learn which part executes work, which part communicates with memory, and why a six-byte queue can let both parts work at the same time.
Two cooperating units
The 8086 is commonly explained as two cooperating units:
- The Execution Unit (EU) decodes instruction bytes, controls execution, performs arithmetic and logic, and updates general registers and flags.
- The Bus Interface Unit (BIU) forms addresses, fetches instruction bytes, transfers memory or I/O data, and maintains the instruction prefetch queue.
This division is a learning model of the chip's organization, not two independent processors. An instruction that reads memory needs both units: the EU determines what the instruction requires, while the BIU performs the external bus transfer.
The diagram separates responsibility, not every physical wire. In particular, the BIU uses segment information and the instruction pointer to obtain instruction bytes; Section 4.2 introduces those programmer-visible registers.
Lab 1 — route responsibilities to the correct unit
Assign each operation to the EU or BIU. The live unit panels reveal why decoding, arithmetic, address formation, and bus control cannot all be treated as the same job.
Check your understanding
Why fetch before the EU asks?
Many instructions take time to decode and execute. During some of that time, the external bus would otherwise be idle. The BIU uses available bus time to prefetch upcoming instruction bytes and place them in a first-in, first-out queue.
The 8086 instruction queue can hold six bytes. “Six bytes” does not mean six instructions: an 8086 instruction can contain one byte or several bytes. The EU removes however many bytes the current instruction needs.
Prefetch creates a simple overlap:
1. The BIU fetches future instruction bytes when the bus is available and the queue is not full.
2. The EU consumes bytes already in the queue and executes the current instruction.
3. While the EU works internally, the BIU may refill the queue.
This is an early form of pipelining, but it is not the deep instruction pipeline found in later processors. The two units overlap only when their resource needs allow it.
When the overlap stops helping
The queue smooths differences between fetching and execution, but it cannot remove every delay:
| Event | Queue consequence | EU consequence |
|---|---|---|
| Queue full | BIU stops prefetching | EU can continue |
| EU consumes faster than BIU refills | Queue becomes empty | EU waits for instruction bytes |
| Operand memory or I/O transfer | Bus is used for data, so prefetch pauses | EU waits if it needs the result |
| Taken jump, call, return, or interrupt | Old queued bytes no longer belong to the correct path and are discarded | Execution restarts from the new stream |
A queue flush is necessary for correctness. Suppose the queue contains bytes after a conditional jump and the jump is taken. Those bytes belong to the fall-through path; executing them would run the wrong program.
Do not interpret the queue as a cache. It is small and sequential, it does not retain arbitrary reusable memory blocks, and a control-flow change discards its stale contents.
Lab 2 — keep the queue useful under pressure
Change the teaching model's fetch rate, EU consumption rate, data-bus pressure, and branch time. Try to prevent starvation, deliberately cause it, and observe exactly how many prefetched bytes a branch discards. The model uses abstract time slots to expose cause and effect; they are not literal fixed 8086 clock cycles.
Check your understanding
A reliable way to reason about the organization
For each event, ask three questions:
1. Who decides? Instruction decoding and ALU control belong to the EU.
2. Who crosses the chip boundary? Memory and I/O bus operations belong to the BIU.
3. What happens to prefetched bytes? They remain in FIFO order unless a new instruction stream makes them stale.
Next, we open the programmer-visible state shared by this work: general registers, pointer and index registers, segment registers, the instruction pointer, and FLAGS.