13.3 UART and 8251 Serial Communication

A processor handles a byte as several bits at once, but a serial wire carries those bits one after another. A universal asynchronous receiver/transmitter (UART) converts between the CPU's parallel bytes and a timed serial waveform. The Intel 8251 is a universal synchronous/asynchronous receiver/transmitter (USART); this section first uses its asynchronous behavior, where no separate clock wire accompanies each data bit.

Build and decode an asynchronous frame

An idle asynchronous line is logic 1. A frame begins with a logic-0 start bit, continues with five to eight data bits sent least-significant bit first, may include a parity bit, and ends with one or more logic-1 stop bits. Both endpoints must agree on baud rate and format before the receiver can locate and interpret the same bit cells.

Baud rate is the number of signaling intervals per second. For the simple binary signaling used here, one baud carries one bit, so

An 8-data-bit frame with one start bit, one parity bit, and one stop bit occupies 11 bit times. At 9600 baud its transmission time is about $11/9600=1.146$ ms, even though it delivers only one eight-bit payload byte.

With even parity, the total number of 1 bits across data and parity must be even; odd parity requires an odd total. A parity mismatch detects some corrupted frames but does not identify the damaged bit and cannot detect every multi-bit error. A low stop-bit sample causes a framing error. If transmitter and receiver baud rates differ, sample positions drift across the frame and can eventually produce wrong data or a framing error.

The frame scope below lets you edit the payload and format, inject a line error, and then compare transmitted bits with the receiver's decoded byte and status.

Operate the 8251 through mode, command, and status

After reset, the 8251 expects a mode word. In asynchronous operation it selects the clock factor, character length, parity, and stop-bit length. Later control writes are command words that enable or disable transmitter and receiver operation, control modem signals, reset error flags, or return the device to its initial state.

The data path has separate transmit and receive sides:

• Software writes a byte only when TxRDY says the transmit buffer can accept it.

• Hardware serializes that byte and reports TxEMPTY only when both the buffer and shift register are empty.

• The receiver assembles a complete frame, places its byte in the receive buffer, and asserts RxRDY.

• Software must read the receive buffer before the next completed byte overwrites it, or overrun error (OE) is set.

Status bits are evidence, not decoration. TxRDY=1 authorizes a new data write; RxRDY=1 demands a data read; PE, OE, and FE identify parity, overrun, and framing failures. Software may poll these bits or connect ready outputs to the Chapter 12 interrupt system. Interrupts change when software is notified, but they do not remove the need to read the status and data registers correctly.

Two endpoints can each be internally correct yet fail as a link if their baud, character length, parity, or stop settings disagree. The terminal lab models both ends, exposes mismatches, and lets the receive buffer overflow when software neglects it.

Section 13.3 turned bytes into timed frames and used status flags to preserve them. Section 13.4 crosses a different boundary: between continuous physical quantities and finite digital codes.