8.2 Datapath, Registers, and ALU

Section 8.1 named the information each instruction phase needs. A datapath is the collection of storage elements and routes that physically carry that information: registers, internal buses, multiplexers, temporary latches, shifters, and the arithmetic logic unit.

Combinational routes produce values; registers preserve state

A register holds a bit pattern across clock cycles. A combinational circuit produces an output from its current inputs without remembering an earlier value. The ALU is combinational; a register is state.

A multiplexer selects one of several candidate inputs. Control signals can select AX for ALU input A, BX for input B, ADD as the ALU function, and CX as the destination. The route implements the register-transfer statement:

An ALU output can change as soon as its inputs or function change. The destination register changes only when its write enable is active at the capturing clock edge. This prevents every temporary value on an internal route from becoming permanent state.

For AX=0003H and BX=0004H, selecting AX, BX, ADD, and CX places 0007H at CX's input. If CXWrite=0, CX remains unchanged. If CXWrite=1 at the edge, CX becomes 0007H.

Data, destination, and flags have separate control paths

An instruction can fail in several distinguishable ways:

• A wrong source selector feeds the ALU an unintended operand.

• A wrong ALU function performs a different transformation.

• A wrong destination decoder writes a correct result to the wrong register.

• A missing register write enable produces a temporary result but commits nothing.

• A missing flag write enable commits the data result while leaving status flags stale.

These faults have signatures. For FFFFH+0001H, correct output is 0000H with CF=1 and ZF=1. If the B selector accidentally chooses AX, the ALU calculates FFFFH+FFFFH=FFFEH. If destination decode chooses CX, AX remains FFFFH while CX becomes 0000H. If only FlagWrite is missing, AX looks correct but a later conditional branch reads old flags.

Temporary internal registers also matter. A memory read may first place data into a memory-data latch, often called MDR in teaching datapaths, before a later route transfers it to AX. These internal names describe implementation roles and may not be programmer-visible 8086 registers.

Good diagnosis observes the complete architectural contract: intended destination, preserved sources, flags, IP, and memory side effects. A numerically correct AX does not prove the entire instruction worked.

The datapath provides possible routes, but it does not decide when to select them. Section 8.3 introduces the control unit and the smaller micro-operations that activate those routes in a safe order.