14.2 Integrating Memory and Peripherals
An architecture names blocks; integration gives each block an address and proves that only the intended block responds during a bus cycle. The capstone uses a 16-bit address space from 0000H through FFFFH. Every byte address must select zero or one device—never two.
Allocate regions and derive chip-select behavior
An address map assigns non-overlapping ranges to ROM, RAM, and peripheral registers. If a device occupies consecutive bytes beginning at base , its final address is
The base must usually align to the region size so simple high-bit decoding can select it. A 256-byte UART region beginning at 8000H ends at 80FFH; the low eight address bits select registers inside the region, while the higher bits identify the device.
An overlap asserts two chip selects for one address. On a read, both devices may drive the data bus and create contention. A gap is not automatically wrong—unassigned addresses can be reserved—but software must not assume they store data. Aliasing occurs when incomplete decoding makes one physical register respond at several addresses. It can be deliberate for cheap hardware, but it complicates debugging and future expansion.
Verify ownership, timing, width, and completion on every cycle
A valid address does not guarantee a valid transfer. A bus cycle must also agree on:
- Owner: CPU or DMA, but not both.
- Direction: exactly one source drives the data bus during a read; the target samples during a write.
- Width: an 8-bit peripheral on a 16-bit data bus must use the intended byte lane or adapter.
- Timing: slow devices need wait states so data is valid before the CPU samples.
- Completion: ready, acknowledgement, timeout, or bus-error behavior must be defined.
Suppose the CPU samples after two cycles but an ADC register needs four. Without two inserted wait cycles, the read may return a previous value or undefined bus level. Adding waits indiscriminately is safe but slows every transfer; decoding should apply them only to the slow target.
Interrupt and DMA wires require the same discipline. A level-triggered interrupt must remain asserted until its source is cleared. A DMA request must map to the configured channel, direction, width, and buffer. The bus debugger exposes premature sampling, double drivers, wrong byte lanes, and missing completion rather than reducing integration to an address table.
Section 14.2 proved that every transfer selects one target, one driver, and a valid sampling instant. Section 14.3 builds software that services those transfers under load and verifies the resulting deadlines and invariants.