14.4 Modern x86, ARM, and SoC Perspective

The 8086, 8259, 8237, and 8251 make system boundaries visible as separate chips and wires. Modern processors integrate many of those roles, but the questions learned in this course remain: who owns an address, which event requests service, when is data valid, and what state must software preserve?

Map familiar mechanisms onto modern platforms

Modern x86 systems retain a separate I/O-port address space for instructions such as IN and OUT, while also using memory-mapped device registers. Advanced Programmable Interrupt Controllers (APICs) replace the simple 8259 model for multicore routing, and platform DMA engines or bus-mastering devices replace the original 8237 for most high-throughput transfers.

Most ARM systems use memory-mapped I/O (MMIO): peripheral registers occupy addresses in the processor's memory map and are accessed with load/store instructions. A Generic Interrupt Controller (GIC) routes interrupts among cores. A system-on-chip (SoC) places CPU cores, timers, serial controllers, DMA engines, memory controllers, and often ADC/DAC blocks on one silicon device connected by an internal interconnect.

Integration changes implementation scale, not the need for a contract. An MMIO register may have read-to-clear bits or reject ordinary caching. An interrupt controller must target a core and priority. A DMA engine still needs direction, length, ownership, completion, and an address it is permitted to access.

The migration planner asks the learner to select a platform and then choose compatible register access, interrupt routing, DMA, and timer mechanisms. Incorrect mixtures—such as assigning an 8259-specific EOI sequence to a GIC-only system—remain visible as contract failures.

Make CPU caches and DMA agree about memory

A modern CPU usually reads and writes through a cache, a small fast copy of recently used memory. A DMA device may access main memory directly. On a non-coherent path, these two observers can temporarily see different values:

1. The CPU writes a transmit buffer only into a dirty cache line.

2. DMA reads older main-memory bytes and sends stale data.

3. Alternatively, DMA writes a receive buffer in memory while the CPU continues reading an old cached copy.

A cache clean writes dirty CPU data back to memory before device read. A cache invalidate discards stale CPU copies after device write. A memory barrier constrains the order in which operations become observable; it does not by itself copy cache contents. Coherent systems automate more visibility, but software still follows ownership and ordering rules defined by the platform.

An IOMMU can translate and restrict device-visible addresses, providing protection similar in purpose to CPU memory translation. It does not automatically fix stale cache data. Security, multicore concurrency, virtualization, and speculative execution add constraints, yet the diagnostic method is familiar: identify owner, address, cached copy, ordering point, completion event, and evidence.

The coherency lab exposes separate cache and memory values. Learners can deliberately start DMA too early, then repair transmit and receive sequences with clean, barrier, completion, and invalidate operations.

The course began with individual bits and ended with a complete, verified system. Processor generations change, but disciplined reasoning about representation, addresses, timing, ownership, events, and evidence remains transferable.