3.2 Decoders, Multiplexers, and ALUs
Section 3.1 combined gates into larger truth-table rules. Real processors reuse several especially useful combinations. This section develops three of them from zero:
- a decoder activates one destination;
- a multiplexer chooses one source;
- an arithmetic logic unit (ALU) computes several candidate operations and exposes the selected result.
A decoder turns a binary code into one selected line
A decoder reads an -bit input code and can distinguish up to outputs. A 2-to-4 decoder reads address bits A1A0 and controls Y0 through Y3.
When enable input EN is 1, exactly one output is active. This is called one-hot output.
| EN | A1A0 | Y0 | Y1 | Y2 | Y3 |
|---|---|---|---|---|---|
| 0 | any | 0 | 0 | 0 | 0 |
| 1 | 00 | 1 | 0 | 0 | 0 |
| 1 | 01 | 0 | 1 | 0 | 0 |
| 1 | 10 | 0 | 0 | 1 | 0 |
| 1 | 11 | 0 | 0 | 0 | 1 |
“Any” means the address does not matter while EN=0. The enable signal lets a larger system turn the entire decoder on or off.
Later, address-decoding circuits will use this idea to select memory chips and I/O devices.
Lab 1 — dispatch a request to one device
Translate a device number into two address bits, control EN, and observe the one-hot output lanes.
Check your understanding
A multiplexer chooses one input source
A multiplexer, often shortened to MUX, has several data inputs but one output. Select bits determine which input is connected logically to the output.
For a 4-to-1 MUX:
| S1S0 | Output Y |
|---|---|
| 00 | D0 |
| 01 | D1 |
| 10 | D2 |
| 11 | D3 |
The MUX does not combine all four inputs. It routes one of them. If D2 changes while S1S0=00, Y does not change because D0 remains selected.
An ALU computes candidate operations
An arithmetic logic unit is a combinational block that performs arithmetic and bitwise logic. A simple 4-bit ALU might support:
| Select | Operation | Example with A=1010, B=1100 |
|---|---|---|
| 00 | AND | 1000 |
| 01 | OR | 1110 |
| 10 | XOR | 0110 |
| 11 | ADD | 0110, with carry 1 |
The operation blocks can produce candidates in parallel. A MUX controlled by the select bits exposes one candidate as the ALU result.
The ALU may also produce status signals. Two useful examples are:
- carry flag (CF): addition produced a bit beyond the fixed width;
- zero flag (ZF): every result bit is 0.
Chapter 2 already showed why fixed-width addition can wrap. Later chapters will connect these flags to 8086 instructions and conditional branches.
Lab 2 — configure a miniature ALU datapath
Set 4-bit operands and selection signals. Compare all candidate operations, then route the required one while watching CF and ZF.
Check your understanding
Distinguish the three blocks
| Block | Main question | Data direction |
|---|---|---|
| Decoder | Which destination should be active? | one code → one of many output lines |
| Multiplexer | Which source should reach the output? | one of many inputs → one output |
| ALU | Which transformation should be applied? | operands → selected arithmetic/logic result |
All three blocks are combinational: current inputs determine current outputs. A processor also needs hardware that keeps a value after the input changes. That requires state and feedback, which begin with latches and flip-flops.