1.4 Buses and System Organization

CPU, memory, and I/O must exchange many bits, but dedicating separate wires to every possible pair would be wasteful. A bus is a shared group of signal lines used to carry related information between components.

The word “bus” may describe physical conductors, the signals on them, and the rules governing a transfer. In this first model, divide the system bus into three functional families.

Address bus: which location or device?

The CPU uses address signals to select a memory location or I/O register. If there are \(n\) independent binary address lines, they can form \(2^n\) distinct bit patterns.

For example:

• 8 address lines select up to \(2^8 = 256\) addresses;
• 16 address lines select up to \(2^{16} = 65{,}536\) addresses;
• 20 address lines select up to \(2^{20} = 1{,}048{,}576\) addresses.

This is a count of addressable locations, not automatically a count of bytes. If each address identifies one byte, 16 address lines describe a 64 KiB byte-addressed space. Other organizations are possible.

In a basic single-CPU system, address information usually travels from the CPU toward memory and I/O.

Data bus: what value?

The data bus carries the value being transferred. Its direction depends on the operation:

• during a read, the selected memory or I/O device sends data toward the CPU;
• during a write, the CPU sends data toward the selected memory or I/O device.

An 8-bit data bus can carry 8 bits in one transfer. Moving a 16-bit value may require two transfers on that bus. A wider bus can move more bits at once, but needs more physical signal lines and supporting circuitry.

Exactly one intended sender should normally drive a shared data bus at a time:

• contention occurs when two outputs try to drive conflicting values;
• a floating bus has no active sender and therefore no guaranteed valid value.

Real hardware uses controlled output stages and precise timing to avoid these states.

Control bus: what action, and when?

Control signals give the other signals context. Typical examples include:

• read and write signals;
• a clock or timing reference;
• reset;
• interrupt requests;
• ready or wait indications.

A bit pattern on the data lines does not announce whether it is being read or written. Address, data, and control must form one coherent bus transaction.

Lab 1 — direct shared-bus traffic

Configure a memory read, memory write, or I/O read. You control the target, read/write signals, and both possible data drivers. The bus view immediately reports direction, floating state, or contention.

For each mission, say the rule before touching a switch: “the owner of the source data must drive the bus.” Then verify that only that sender is active.

Worked transactions

Memory read from address 0x20

1. CPU places 0x20 on the address bus. 2. CPU asserts the read control signal. 3. Address-decoding logic selects memory. 4. Selected memory drives the requested value onto the data bus. 5. CPU captures the value. 6. The signals return to their inactive state.

Memory write of 0x5A to address 0x20

1. CPU places 0x20 on the address bus. 2. CPU places 0x5A on the data bus. 3. CPU asserts the write control signal. 4. Selected memory captures the value. 5. The signals return to their inactive state.

Compare the direction of the data bus. Address still identifies the destination, but the data sender changes.

Width, timing, and pin trade-offs

Bus design affects both capability and physical cost.

Address width

More address lines make more unique locations selectable. This increases possible memory or I/O space, but adds pins and decoding circuitry.

Data width

More data lines transfer more bits per bus operation. They may reduce the number of transfers for a large value, but add pins and wiring.

Clock and wait states

Fast processors may be connected to slower devices. A wait state extends a transaction so the selected device has time to respond. Removing every wait state is not correct if the hardware cannot meet the shorter timing.

Multiplexing

Some processors reuse the same pins for address information during one part of a transaction and data during another. This multiplexing reduces pin count but requires timing control and usually an external latch to preserve the address.

There is no universally best bus. A battery sensor, a fast firmware loader, and a laboratory instrument value different combinations of cost, speed, compatibility, and package size.

Lab 2 — design a bus under constraints

Choose address width, data width, clock, wait states, and address/data multiplexing. The lab calculates address space, estimated pins, transfer cycles, and time for three different missions.

After satisfying a mission, change only one choice. Identify the first broken constraint and explain the causal chain—for example, narrower data means more transfers, which means more cycles and more time.

Chapter 1 synthesis

A microcomputer is an organized system:

stored program in memory
          ↓
CPU fetches → decodes → executes
          ↓
address selects · control names the action · data carries the value
          ↓
memory and I/O preserve, observe, or act

You can now distinguish a processor from a complete computer, assign roles to CPU/memory/I/O, trace the instruction cycle, and reason about a bus transaction. Chapter 2 will build the bit-level number and data representations that give bus and memory patterns precise meaning.