10.3 Memory Banks and Capacity Expansion
Section 10.2 selected one memory chip. A complete 8086 memory system must also connect byte-wide chips to its 16-bit data bus and combine packages when one chip is not wide or deep enough.
Even and odd banks match the 8086 data bus
Memory is byte-addressable: each address names one byte. The 8086 nevertheless transfers as many as 16 bits at once, so its memory is commonly divided into two byte-wide banks:
- The even, low bank connects to D7…D0. A0 low selects it.
- The odd, high bank connects to D15…D8. Active-low
/BHE(bus high enable) selects it.
Because A0 helps choose a bank, the shared bank-address path begins with A1 rather than A0. Its lower bits select a location inside a chip, while its higher bits participate in chip decoding. The same value on A19…A1 identifies a pair of neighboring bytes: the low bank holds the even-addressed byte and the high bank holds the following odd-addressed byte.
| A0 | /BHE | Selected bank or banks | Typical transfer |
|---|---|---|---|
| 0 | 1 | Low only | Byte at an even address |
| 1 | 0 | High only | Byte at an odd address |
| 0 | 0 | Both | Word starting at an even address |
| 1 | 1 | Neither | No memory byte selected |
An aligned word begins at an even address. Both bytes share one bank address, so the processor can select both banks in one bus cycle. A word beginning at an odd address is unaligned: its low byte is in the high bank at one bank address, while its high byte is in the low bank at the next bank address. It therefore needs two bus cycles.
Parallel chips add width; groups add depth
A memory package is described as depth × width. An 8 Ki × 8 chip has 8 Ki addressable locations, each holding 8 bits. A required memory array may exceed either dimension.
- Connect chips in parallel to increase width. They share address and control signals but connect to different data lanes.
- Add separately selected groups to increase depth. The low address bits select a location within every group; a decoder uses higher bits to enable exactly one group.
Suppose a design needs 32 Ki × 16 memory from 8 Ki × 8 chips:
Each group contains two parallel chips for a 16-bit word, and four decoded groups provide the required depth. The two width chips share the same chip-select because their data outputs occupy different lanes; the four depth groups must never be selected together.
Banks and chip groups describe the hardware. Section 10.4 places those groups into one non-overlapping address map and previews why frequently used memory is often copied into a cache.