8.4 Instruction Timing and Performance

Section 8.3 arranged work into control time slots. Real hardware must also allow signals enough time to propagate before the next clock edge. Timing analysis connects the physical delay of one slot to the execution time of a complete workload.

The critical path sets the shortest safe clock period

After a source register launches a value, the value passes through combinational logic before a destination register captures it. The destination input must become stable early enough to satisfy the register's setup time.

In a simplified timing budget:

T_{\text{clock}}\geq t_{\text{launch}}+t_{\text{combinational}}+t_{\text{setup}}+t_{\text{margin}}

The critical path is the longest path that must finish within one clock cycle. It determines the minimum safe clock period and therefore the maximum safe clock frequency:

f_{\max}=\frac{1}{T_{\min}}

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Suppose a register-add path needs 1+4+1+1=7 ns, while a memory-load path needs 1+5+1+1=8 ns. With one shared clock, the memory-load path is critical, so 8 ns is the shortest safe period. Its theoretical ceiling is:

f_{\max}=\frac{1}{8\ \mathrm{ns}}=125\ \mathrm{MHz}

Timing slack measures the unused part of the period:

\text{slack}=T_{\text{clock}}-T_{\text{required}}

Positive slack is safe in this model, zero slack exactly meets the budget, and negative slack is a timing violation. At a 7 ns period, the register-add path has zero slack but the memory-load path has −1 ns. The clock cannot be chosen from an average path delay; every required path must meet timing.

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Program time combines instruction count, CPI, and clock rate

Clock frequency alone does not determine processor performance. For a particular workload:

T_{\text{CPU}}=\text{instruction count}\times\text{average CPI}\times T_{\text{clock}}

Equivalently:

T_{\text{CPU}}=\frac{\text{instruction count}\times\text{average CPI}}{\text{clock frequency}}

CPI means cycles per instruction. Instructions can have different CPIs, so a workload uses a weighted average:

\mathrm{CPI}_{\text{avg}}=\sum_i \left(\text{instruction fraction}_i\times\mathrm{CPI}_i\right)

Wait states, branch behavior, memory traffic, and prefetch success can change the effective CPI. On the 8086, the BIU can prefetch instruction bytes while the EU executes, but a control transfer or a busy bus can reduce that overlap. The equation still applies; these effects appear in the measured or modeled average CPI.

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For 100,000 instructions, a 5 MHz reference CPU with CPI=4 takes:

T_{\text{ref}}=\frac{100{,}000\times4}{5{,}000{,}000}=80\ \mathrm{ms}

A candidate at 8 MHz has base CPI=3. If 50% of its instructions each add two memory wait cycles, its average CPI is 3+0.50×2=4, and it takes 50 ms. The speedup is:

\text{speedup}=\frac{T_{\text{old}}}{T_{\text{new}}}=\frac{80}{50}=1.6

This example also separates latency from throughput. Latency is the time for one task or instruction to finish; throughput is the amount of work completed per unit time. Overlap can improve throughput without shortening every individual instruction's latency.

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Chapter 8 has connected instruction phases, datapath routes, control signals, and timing. Chapter 9 will move outward to the bus cycles that carry processor requests to memory and I/O devices.

8.4 Instruction Timing and Performance

The critical path sets the shortest safe clock period

In a simplified timing budget:

T_{\text{clock}}\geq t_{\text{launch}}+t_{\text{combinational}}+t_{\text{setup}}+t_{\text{margin}}

The critical path is the longest path that must finish within one clock cycle. It determines the minimum safe clock period and therefore the maximum safe clock frequency:

f_{\max}=\frac{1}{T_{\min}}

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f_{\max}=\frac{1}{8\ \mathrm{ns}}=125\ \mathrm{MHz}

Timing slack measures the unused part of the period:

\text{slack}=T_{\text{clock}}-T_{\text{required}}

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Program time combines instruction count, CPI, and clock rate

Clock frequency alone does not determine processor performance. For a particular workload:

T_{\text{CPU}}=\text{instruction count}\times\text{average CPI}\times T_{\text{clock}}

Equivalently:

T_{\text{CPU}}=\frac{\text{instruction count}\times\text{average CPI}}{\text{clock frequency}}

CPI means cycles per instruction. Instructions can have different CPIs, so a workload uses a weighted average:

\mathrm{CPI}_{\text{avg}}=\sum_i \left(\text{instruction fraction}_i\times\mathrm{CPI}_i\right)

Rendering diagram…

For 100,000 instructions, a 5 MHz reference CPU with CPI=4 takes:

T_{\text{ref}}=\frac{100{,}000\times4}{5{,}000{,}000}=80\ \mathrm{ms}

A candidate at 8 MHz has base CPI=3. If 50% of its instructions each add two memory wait cycles, its average CPI is 3+0.50×2=4, and it takes 50 ms. The speedup is:

\text{speedup}=\frac{T_{\text{old}}}{T_{\text{new}}}=\frac{80}{50}=1.6

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Chapter 8 has connected instruction phases, datapath routes, control signals, and timing. Chapter 9 will move outward to the bus cycles that carry processor requests to memory and I/O devices.