14.1 Capstone Requirements and System Architecture
Chapter 13 introduced timers, DMA, serial links, and converters separately. The capstone combines them into an environmental controller: it samples a temperature sensor, stores recent samples, accepts serial commands, and drives a fan. Integration begins with measurable requirements, not a parts list.
Convert a goal into budgets that can be tested
A statement such as “measure temperature reliably” is a goal. A requirement adds an observable condition and a limit: “capture one 10-bit sample every 1 ms, preserve the newest 256 samples, and update the fan within 5 ms of crossing 70 °C.” A test can decide whether this sentence is true.
Requirements create linked budgets:
- A 1 ms sample period means a 1 ksample/s arrival rate.
- Two bytes per stored sample require 2 kB/s of memory bandwidth and 512 bytes for a 256-sample buffer.
- At 115200 baud with 8N1 framing, each payload byte consumes 10 bit times, so the practical ceiling is 11520 bytes/s before protocol overhead.
- A 5 ms response deadline includes conversion, interrupt waiting, software execution, and DAC update—not just one ISR.
Budgets expose impossible combinations early. A 9600-baud link cannot continuously transmit 2000 payload bytes each second with 8N1 framing because its ideal payload ceiling is only 960 bytes/s. The design must reduce reporting rate, compress data, raise baud rate, or change the requirement.
Partition responsibilities and define every interface
An architecture assigns each responsibility to hardware or software and defines how blocks exchange control, status, and data. In this capstone:
- A timer provides the sample trigger.
- An ADC converts sensor voltage to a code.
- DMA moves codes into a circular memory buffer without one CPU instruction per sample.
- The interrupt controller reports buffer milestones and UART events.
- Foreground software calibrates samples, parses commands, and chooses a fan command.
- A DAC converts that command to actuator voltage.
Every arrow needs an interface contract: producer, consumer, units, rate, width, ownership, readiness, and error behavior. “ADC connects to DMA” is incomplete until the design identifies the ready request, data width, destination address, count, and terminal-count action. A boundary diagram also prevents hidden responsibilities. Calibration belongs in software; voltage protection and range conditioning belong before the ADC.
Architecture review looks for missing paths, duplicated ownership, and circular assumptions. If both the CPU and DMA can write the same buffer position without coordination, the blocks exist but the system is not safe. The builder below makes interface omissions and ownership conflicts observable.
Section 14.1 established measurable contracts and assigned responsibilities. Section 14.2 turns that architecture into one conflict-free address map and one electrically valid shared bus.