9.2 Read, Write, and Acknowledge Cycles
Section 9.1 identified the three kinds of bus information. They cannot change arbitrarily. A bus cycle is the timed sequence that performs one external transfer. A basic 8086 cycle uses clock states T1, T2, T3, and T4; a state name identifies a timing interval, not a separate machine instruction.
T1 through T4 establish, transfer, and release
A simplified zero-wait read cycle proceeds as follows:
1. T1 — Address: the processor drives the address. ALE marks the interval in which external latches may capture the multiplexed address.
2. T2 — Command and turnaround: the processor stops driving the multiplexed pins as address outputs, configures the data path to receive, and asserts /RD.
3. T3 — Data and completion: the selected device drives valid data. READY indicates that the transfer may complete.
4. T4 — Finish and release: the read value has been captured at the completion boundary; the processor deasserts the command and releases or prepares the interface for another cycle.
A write uses the same four-state frame but reverses data ownership. The CPU supplies the address in T1, then drives write data and asserts /WR in T2. It keeps the data stable through the device's required capture interval. In T4 it deasserts /WR and releases the transfer.
The T2 interval matters especially during a read. The AD pins carried address from the CPU in T1, but the device must drive those pins with data later. The CPU must stop driving before the device begins. This non-overlap is called bus turnaround.
Completion must follow valid address, command, and data
An acknowledgment is evidence that a receiver can complete a requested transfer. Buses use different signal names and handshakes for this idea. On the 8086 interface, READY is the important pacing input: if the selected memory or I/O device is not ready at the required sampling point, the processor extends the current cycle with one or more wait states.
READY does not mean “skip the remaining rules.” It is valid only after the earlier conditions are satisfied:
- the intended address has been preserved;
- the correct read or write command is active;
- exactly one endpoint drives the data bus; and
- read data is stable for capture, or write data has been accepted.
This ordering makes logic-analyzer traces diagnosable. Several faults have distinct signatures:
- Missing ALE can lose the address when multiplexed pins change to data.
- Two data drivers create contention even if READY is late enough.
- READY asserted before read data stabilizes can make the CPU capture an indeterminate value.
/WRremaining active after T4 can extend a write beyond its intended boundary.
Adding wait states repairs only a timing shortage. It cannot repair a wrong address, a read/write reversal, or two enabled output drivers. A correct diagnosis first classifies the fault as selection, direction, timing, or release.
The 8086 also has interrupt-acknowledge bus activity, but that is a specific control transaction studied with interrupts in Chapter 12. Here, “acknowledge” describes the general completion relationship represented by READY, not a claim that every read or write produces a separate ACK data packet.
Section 9.2 has treated the AD pins as address in T1 and data later. Section 9.3 explains the hardware that makes this role change possible: address latches, bidirectional transceivers, and tri-state outputs.