10.2 Address Decoding and Chip Select
Section 10.1 described memory technologies. A system normally contains several chips, so an address must select both one chip and one location inside that chip. Address decoding converts an address pattern into a chip-select signal.
Low bits select a location; high bits select a chip
An 8 KiB byte-wide chip contains locations, so it uses A12…A0 as its internal offset. If mapped at 20000H, its inclusive window is:
The remaining high bits A19…A13 must match the pattern for that window. When they match, /CS becomes active; otherwise the chip ignores read and write commands.
A power-of-two-sized window should start at a multiple of its size. Alignment makes low bits mean only offset and high bits mean only selection, producing clean boundaries.
Incomplete decoding creates aliases
Full decoding compares every address bit not used inside the chip. Partial decoding ignores one or more high bits to save logic. It may still operate electrically, but the same physical chip then appears at multiple CPU address ranges.
If a 4 KiB chip uses A11…A0 internally and the decoder ignores A15…A12, those four bits have combinations. One physical cell therefore has 16 external alias or mirror addresses.
Aliases may be intentional in a tightly controlled design, but they complicate memory maps and can hide decoder mistakes. Worse, two different chips may be selected together if their partial-decode conditions overlap.
Decoder verification probes both sides of every boundary and varies each supposedly significant high bit. A correct full decoder selects every address inside its window, rejects the first address outside each edge, and produces no unexpected mirrors.
Section 10.2 selects one chip. Section 10.3 combines several chips to match the 8086 data width and to build more locations than one package provides.