9.3 Multiplexing, Latches, and Tri-State Buffers

Section 9.2 used the same AD15…AD0 pins for an address in T1 and for data later. This is time multiplexing: one physical route carries different kinds of information in different time intervals. Multiplexing saves package pins, but the system must preserve the first value before the route changes jobs.

ALE and a latch turn a temporary address into a stable address

During T1, the 8086 places address bits A15…A0 on AD15…AD0. It also places the high address bits on A19/S6…A16/S3, which later carry status information. ALE, or Address Latch Enable, identifies the address-valid interval.

A latch is a storage circuit. While enabled it can observe its input; when the enable closes, it holds the captured bit pattern at its output. External latches use ALE so the system retains the address after the processor pins change to data or status.

For address 3A55AH:

• A19…A16 contributes 3H;

• AD15…AD0 contributes A55AH during T1; and

• the demultiplexed address is their concatenation, 3A55AH.

If AD15…AD0 later carries data C0DEH, the latch output remains A55AH. The device therefore sees stable address 3A55AH at the same time that it sees data C0DEH.

Capturing too late produces a structural error, not merely a small delay. If the latch captures C0DEH after the pins have changed roles, external logic combines the wrong low bits with the high address bits and selects a different location.

A tri-state output can drive 0, drive 1, or disconnect

Ordinary logic descriptions often mention only 0 and 1. A shared bus needs a third output condition: high impedance, written Z. In Z, the output is electrically disconnected enough that another component may control the wire.

Z is not a third data value stored by the CPU, and it is not the same as logic 0:

• Output 0 actively drives a low voltage.

• Output 1 actively drives a high voltage.

• Output Z stops defining the wire's voltage.

If every output is Z, the bus is floating and has no guaranteed data value. If two outputs are enabled and attempt different values, bus contention occurs. Contention can corrupt data, draw excessive current, and stress hardware.

A bidirectional bus transceiver combines direction control with tri-state output control. On a minimum-mode 8086 system, DT/R selects transmit or receive direction and /DEN enables the external data path. During a write, the CPU side transmits. During a read, the transceiver reverses so the CPU receives. During turnaround or idle, disabling the transceiver creates a deliberate Z interval.

Receivers may listen without becoming drivers. Many devices can observe the address and control buses, but only the selected source may enable its data output. Selection logic, direction control, and output enable must therefore agree.

“Both outputs currently carry the same value” is not a safe exception. Propagation delays and later bits can make the outputs disagree, and the design would no longer enforce ownership. Correct wiring proves a single-driver rule for every phase, not only for one observed pattern.

Latches preserve the target and tri-state controls preserve electrical ownership. Section 9.4 handles two remaining forms of sharing: a slow device that needs more time and another bus master that needs temporary ownership.