3.4 Counters, Clocks, and Timing

Section 3.3 introduced storage that changes at clock edges. Repeating those edges creates a sequence of discrete moments when a system may advance. Counters make that sequence visible.

A clock provides repeated timing events

A clock alternates between 0 and 1. Three terms describe it:

Frequency and period are reciprocals:

For example, a 1 MHz clock completes one million cycles per second, so its period is 1 μs. A clock does not by itself make every operation instantaneous; circuits still need time for signals to propagate and settle.

A counter advances through a state sequence

A counter is a register whose next-state logic follows a planned sequence. A 3-bit up-counter normally visits:

The modulus is the number of distinct states in the repeating cycle. A 3-bit binary counter is normally modulo 8 because $2^3=8$. A decade counter is modulo 10: it counts 0 through 9 and then returns to 0 even if four storage bits could represent 10 through 15.

An enable input can make the counter hold instead of advance. A down-counter moves through the sequence in the opposite direction.

Counter bits divide frequency

In a binary up-counter:

• Q0 changes on every count;

• Q1 changes every two counts;

• Q2 changes every four counts.

Therefore each successive bit has half the toggle frequency of the previous bit. This makes counters useful for frequency division and timed events as well as counting objects.

Lab 1 — design and trace counter cycles

Choose modulus, direction, and enable. Issue pulses individually and inspect how count values and Q3…Q0 evolve, pause, and wrap.

Check your understanding

Storage needs data to be stable near an edge

A flip-flop cannot sample a changing input with unlimited speed. Two constraints define a protected interval around the active clock edge:

• setup time: D must already be stable for a minimum time before the edge;

• hold time: D must remain stable for a minimum time after the edge.

Suppose setup time is 10 ns and hold time is 5 ns. If the active edge occurs at time 0, D must not change during the interval from −10 ns through +5 ns.

A transition inside this protected interval is a timing violation. The flip-flop may enter metastability, a temporary condition in which its internal state takes unusually long to resolve. The correct engineering conclusion is not “it always captures the old value” or “it always captures the new value.” The captured result and resolution time are not guaranteed.

Lab 2 — place transitions around a sampling edge

Move a data transition across setup, clock-edge, and hold regions. Construct safe cases and both kinds of violations while the waveform and diagnosis update together.

Check your understanding

Propagation delay limits clock speed

After a register launches a new value, combinational logic needs time to calculate, and the destination register needs setup time before the next edge. A simplified safe-period condition is:

Real designs also include clock uncertainty and other margins. The important idea is causal: making the clock period shorter does not make the logic itself settle faster. If the next edge arrives too soon, the destination may sample unfinished data.

Chapter 3 synthesis

Chapter 4 will use these building blocks to understand the 8086 as an organized machine: registers hold state, the ALU transforms it, control logic selects paths, and the bus interface fetches instructions and data.