10.4 Memory Maps and Cache Foundations

Section 10.3 built memory hardware from banks and groups. Software needs a simpler view: one address should identify one intended destination. A memory map records which inclusive address range belongs to each device.

Build a complete, non-overlapping memory map

The 8086 has a 20-bit physical address, so its address space runs from 00000H through FFFFFH. A designer partitions that space into allocated, reserved, and currently unallocated regions. For every allocated region:

The +1 matters because both endpoints belong to the region. A plausible map might place 256 KiB of RAM at 00000H–3FFFFH, reserve 40000H–5FFFFH for expansion, leave 60000H–EFFFFH unallocated, and place 64 KiB of ROM at F0000H–FFFFFH. The 8086 begins fetching after reset at physical address FFFF0H, so that address must lead to startup code in the upper ROM.

Two allocated ranges must not overlap. Otherwise a read can make multiple devices drive the bus and a write can modify multiple devices. A hole is different: no device responds there. Holes may be deliberate, but software must not mistake them for memory.

A map review should therefore check inclusive sizes, power-of-two alignment where the decoder requires it, overlap, holes, and special architectural addresses such as the reset location.

A cache trades capacity for speed

The original 8086 has a six-byte instruction prefetch queue, but it does not have an on-chip cache. Cache terminology is introduced here as a foundation for later processors.

A cache is a small, fast store that keeps copies of recently used blocks from a larger, slower memory. It benefits from:

• Temporal locality: recently accessed data is likely to be accessed again.

• Spatial locality: data near a recent address is likely to be accessed soon.

In a simple direct-mapped cache, every memory block has exactly one possible cache line. For a cache with a power-of-two block size and line count:

The index chooses a line. A hit occurs when that line is valid and its stored tag matches; otherwise the access is a miss, and the requested block replaces the line. The first access to a never-loaded block is a compulsory miss. Different active blocks that share an index can repeatedly evict one another, causing conflict misses.

Chapter 10 progressed from memory-cell technology to chip selection, bank construction, full-system mapping, and the basic idea of caching. You can now trace an address from the CPU pins to the particular storage structure that answers it.