11.2 Port Decoding, Polling, and Status

Section 11.1 separated a port address from the data carried through that port. The hardware must now turn the address into exactly one chip-select signal. Software must also avoid reading data before the device has produced it.

Decode control, register, and address bits

A port decoder should check three kinds of information:

• The bus cycle is an I/O cycle of the required direction.

• High address bits match the interface’s assigned base address.

• Low address bits select one register inside the interface.

Suppose an interface occupies 0300H–0303H. Bits A15…A2 identify the four-port window, while A1…A0 select data, status, command, or configuration. A read from 0301H should select only the status register. A memory read from physical address 00301H must not select the interface in an isolated-I/O design.

If a designer ignores required high bits, the same physical registers appear at multiple alias addresses. Aliasing may reduce hardware cost, but it makes the system map ambiguous and can conflict with later devices. Complete decoding is the safe default when address space is not severely constrained.

Poll a status bit without destroying other information

A slow device often exposes a status register. Each bit reports a condition such as ready, busy, error, or data available. Polling means repeatedly reading that register until a required bit reaches the desired value.

If bit 3 is READY, software can isolate it with a mask:

wait_ready:
    IN   AL, DX
    TEST AL, 08H
    JZ   wait_ready

08H has only bit 3 set. TEST performs an AND-like comparison for flags without changing AL. The loop exits when bit 3 is 1. Testing the whole byte for equality with 08H would be fragile: an unrelated error or mode bit could also be 1 even though READY is valid.

Polling is simple but consumes bus cycles and CPU time. A very tight loop finds readiness quickly but wastes more reads; a delayed loop reduces traffic but may react later. Later chapters introduce interrupts and direct memory access as alternatives when waiting cost becomes unacceptable.

Polling works only when the device can safely hold its ready condition until software notices. Section 11.3 adds explicit request-and-acknowledge signals for transfers whose timing cannot be assumed.