13.1 8253/8254 Timers and Counters
Chapter 12 showed how a device can request service when an event occurs. A programmable interval timer creates precisely timed events without making the CPU spend instructions counting. The Intel 8253 and its compatible successor, the 8254, each contain three independent 16-bit counters. Every channel has three visible signals:
CLKsupplies pulses to count.
GATEenables or controls counting, depending on the selected mode.
OUTreports the channel's timed result to another device or an interrupt input.
Turn clock pulses into a useful output
A counter starts from a programmed reload value and changes state on incoming clock edges. In mode 0, OUT begins low and becomes high after the terminal count, making a one-shot delay. In mode 2, OUT produces a one-clock-wide low pulse every clocks, making a rate generator. In mode 3, OUT repeatedly alternates high and low, making an approximately square waveform.
For periodic modes, the repetition frequency is
For example, a 1 MHz clock and produce 1 kHz repetitions. This formula describes repetition rate, not pulse width. Mode 2 produces a narrow low pulse, whereas mode 3 divides the period between high and low intervals. When is odd in mode 3, the high interval is one clock longer than the low interval.
The initial visible state matters. Before a mode-0 terminal count, low OUT means “the delay has not finished”; after completion, high OUT remains asserted. In modes 2 and 3, stopping GATE high-to-low stops the repeating count and forces or preserves OUT according to the mode. A design must therefore specify both the numerical divisor and the electrical meaning of GATE and OUT.
Program the control word and count bytes in order
The 8253/8254 data bus is eight bits wide, but each counter holds 16 bits. Software first writes a control word and then writes one or two count bytes to the selected channel. Its fields are:
| Bits | Meaning |
|---|---|
SC1:SC0 | Select counter 0, 1, or 2 |
RW1:RW0 | Latch count, write/read low byte, high byte, or low then high |
M2:M0 | Select operating mode 0 through 5 |
BCD | Choose 16-bit binary or four-digit binary-coded decimal counting |
The common RW=11 sequence means least significant byte (LSB) first, then most significant byte (MSB). To load 1234H, software writes 34H and then 12H. Swapping the bytes silently loads 3412H, so the counter still runs but at the wrong period. Writing only the first byte leaves the two-byte load incomplete.
A timer register read can be unstable if the count changes between reading its two bytes. A latch command copies the current count into a holding register so both reads describe one instant. The 8254 also adds a read-back command that can latch status and counts from multiple channels. These mechanisms do not stop the physical counter; they create a coherent software snapshot.
A reliable timer bring-up checklist is therefore: calculate , verify its legal range, choose a mode, construct the control word, send bytes in the declared order, establish GATE, and observe OUT. The following workbench deliberately exposes incomplete and reversed writes instead of hiding them.
Section 13.1 converted clock edges into deterministic delays and waveforms. Section 13.2 uses similar hardware autonomy for a larger job: moving whole blocks of data while the CPU temporarily releases the bus.