1.3 Stored Programs and the Instruction Cycle

The hardware of a calculator and the hardware of a simple controller may be similar. What makes them behave differently is the sequence of instructions they execute. The stored-program idea says that those instructions can be represented as patterns of bits and kept in memory.

That idea has a powerful consequence: a system's behavior can change when its program changes, without rebuilding the processor's physical circuits.

Instructions live at addresses

Imagine a tiny memory containing this teaching program:

The named operations are a readable stand-in for bit patterns. A real processor's instruction set architecture defines which bit pattern means LOAD, ADD, or another operation. We will study that boundary later.

This example also uses an accumulator, a CPU register that holds a working value. If memory location 5 contains 4 and location 6 contains 3, the program produces 7.

Three small pieces of CPU state

To follow the cycle, track:

• the program counter (PC): the address of the next instruction to fetch;
• the instruction register (IR): the currently fetched instruction;
• the accumulator (ACC): a working register used by our tiny teaching CPU.

Registers are storage locations inside the CPU. They are much smaller than main memory but immediately available to the processor's circuits.

Fetch, decode, execute

The CPU repeatedly performs an instruction cycle.

1. Fetch

The PC supplies an address. Memory returns the instruction stored at that address, and the CPU copies it into the IR. The PC normally advances to the following address.

IR ← Memory[PC]
PC ← PC + 1

The arrow means “the destination receives a copy of the value on the right.” It is not a mathematical equality.

2. Decode

Control logic examines the instruction in the IR. It identifies the operation and any operand information. Decoding ADD 6, for example, tells the CPU to obtain the value at address 6 and use the addition circuits.

3. Execute

The CPU performs the operation. Execution may:

• change a register;
• read or write memory;
• transfer data to or from an I/O device;
• change the PC;
• halt the processor.

After execution, the CPU normally fetches the instruction named by the current PC.

Lab 1 — become the clock

The clockwork CPU exposes PC, IR, ACC, memory, output, and a trace. Advance one micro-phase at a time, or run a complete instruction and compare what changed.

Before pressing a control, predict the next change. On a fetch, expect IR and PC to change; on ADD, expect ACC to change; on STORE, expect a memory location to change.

A complete trace

With Memory[5] = 4 and Memory[6] = 3, the instruction effects are:

Notice three details:

1. The PC advances during fetch, before the fetched instruction executes. 2. STORE changes memory but does not need to erase the accumulator. 3. HALT changes control state: the processor stops starting new cycles.

The exact behavior depends on the processor design. This trace is an intentionally small model for learning the sequence.

Instructions are data that control later actions

A stored program occupies memory just as other bit patterns do. The CPU treats a fetched pattern as an instruction because it arrived through the instruction-fetch process and its bit fields match the architecture's encoding.

This does not mean every data value should be executed. It means the hardware can read program representation from storage. The program's location and control flow determine which locations are fetched as instructions.

Order matters:

LOAD X → ADD X → ADD ONE → STORE OUT → OUTPUT

computes and displays 2x + 1. If OUTPUT happens before STORE OUT, the display may receive an old value. The same individual instructions in a different order can produce different behavior.

Lab 2 — patch the stored program

Edit the five instruction slots so the program computes 2x + 1. The lab tests several inputs after every edit and shows a complete execution trace for the selected input.

A program that works only for x = 0 is not solved. Use all test cases to distinguish a correct rule from a coincidence, then swap two instructions and explain the failure.

Checkpoint

The stored-program model joins memory and control:

1. instructions are encoded and stored at memory addresses; 2. PC identifies the next instruction; 3. fetch copies it to IR and normally advances PC; 4. decode determines the requested operation; 5. execute changes data, state, I/O, or control flow; 6. the cycle repeats until control flow says otherwise.

So far, arrows in our diagrams have represented abstract transfers. The next section examines the shared electrical pathways—the buses—that make those transfers possible.