9.4 Wait States, Bus Arbitration, and 8086 Modes

Section 9.3 established a single-driver rule. That rule solves electrical overlap, but two practical differences remain: devices do not all respond at the same speed, and the CPU is not always the only component that needs to initiate transfers.

READY stretches one cycle for a slower device

A wait state, written Tw, is an extra clock state inserted into a bus cycle when the selected device cannot meet the normal response deadline. On the 8086, Tw states occur between T3 and T4. They extend the current transfer; they do not create a new address phase.

During Tw:

• the latched address still identifies the same target;

• the active command remains associated with the same read or write;

• the data direction must remain correct; and

• the processor continues to test the synchronized READY condition.

The exact pin-level setup and hold budget depends on the processor speed, clock generator, interface logic, and device. A useful early design model is:

Each Tw adds one clock period to the response window. The smallest safe $N_{Tw}$ meets the device delay with nonnegative slack. Extra waits are electrically safe in this model but reduce throughput.

READY lets one system mix fast and slow devices. Fast memory may finish without a wait, while an older ROM or asynchronous peripheral extends only its own accesses. A fixed worst-case delay on every cycle would waste time on the fast path.

Arbitration transfers ownership at a complete-cycle boundary

A bus master is a component allowed to initiate transfers by driving address and control information. The CPU is normally the master, but a direct memory access (DMA) controller can move data without asking the CPU to execute one instruction per transferred word.

Arbitration decides which requester becomes master. A safe handoff preserves one invariant:

> At any instant, no more than one bus master drives the shared address, data-output, and control resources.

In 8086 minimum mode, a requester uses HOLD and the CPU responds with HLDA:

1. The external controller asserts HOLD.

2. The CPU finishes its current bus cycle if one is active.

3. The CPU floats the shared bus outputs and asserts HLDA.

4. The external master performs its transfers.

5. The requester deasserts HOLD, after which the CPU withdraws HLDA and regains the bus.

Request is not grant. If a DMA controller starts driving immediately after asserting HOLD, it can overlap the CPU's unfinished cycle.

Minimum and maximum mode divide control responsibility differently

The 8086's minimum mode and maximum mode change the meaning of several pins and divide responsibilities differently between the CPU and external controllers.

The MN/MX input selects one of two pin-function sets:

/RD is available in both pin-function sets, while several other pins change meaning. For example, the minimum-mode HOLD and HLDA pins become RQ/GT lines in maximum mode. RQ/GT uses request, grant, and release signaling on a bidirectional line; it is not simply HOLD with a different label.

Maximum mode does not make the processor faster and does not increase address width. It reorganizes control so external bus-control and arbitration components can coordinate a more complex system. Minimum mode keeps a smaller system simpler by generating common controls directly.

Chapter 9 has connected signal roles, bus-cycle timing, multiplexed pins, electrical ownership, variable response time, and mastership. Chapter 10 will use this interface to connect real RAM and ROM chips, decode chip-select signals, and build a complete memory map.