12.2 The 8086 Interrupt Vector Table
Section 12.1 classified interrupt sources, but an event type still needs an address for its handler. The 8086 stores these addresses in the Interrupt Vector Table (IVT), a fixed table at physical addresses 00000H–003FFH.
Resolve an interrupt type into CS:IP
The 8086 supports 256 interrupt types numbered 00H–FFH. Each vector occupies four bytes, so the entry for type begins at:
The first two bytes store IP; the next two store CS. Each 16-bit word is little-endian, so its low byte appears at the lower address.
For type 21H, . If locations 00084H–00087H contain 34H 12H 00H F0H, the words are IP=1234H and CS=F000H. The handler begins at F000H:1234H, whose physical address is F1234H.
The IVT ends at 003FFH because bytes. A type outside 00H–FFH cannot be represented. Writing one vector with the wrong byte order or at the wrong multiple-of-four boundary sends control to an unintended address.
Trace entry state and IRET
An interrupt must preserve the point where foreground execution can continue. Suppose the current state is FLAGS, CS, IP, and SP. On accepted interrupt entry, the 8086:
1. pushes FLAGS;
2. clears IF and the Trap Flag (TF);
3. pushes CS;
4. pushes IP;
5. loads new IP and CS from the selected IVT entry.
Because the stack grows toward lower addresses, the saved IP ends at the top of the stack. IRET reverses the frame by popping IP, then CS, then FLAGS. An ordinary RET restores only an instruction pointer and therefore cannot correctly return from this interrupt frame.
The saved FLAGS word contains the pre-interrupt IF and TF values. Although the live flags are cleared during entry, IRET can restore the earlier state. Corrupting the frame changes the return address or flag state and can make the failure appear only after the handler finishes.
The vector table and stack frame explain where a handler starts and how it returns. Section 12.3 focuses on what the handler must preserve and how multiple pending requests are controlled.