9.1 Address, Data, and Control Buses
Chapter 8 followed values inside the CPU. The processor must also exchange instruction bytes and operands with components outside it. A bus is a shared set of signal lines plus rules for using them. “Shared” means several components connect to the same route, not that all of them may transmit at once.
One transfer must answer where, what, and which action
Three signal groups cooperate in an external transfer:
- The address bus identifies a memory location or I/O port: where.
- The data bus carries the payload being read or written: what.
- The control bus identifies the operation and its timing: which action, in which direction, and when.
For example, a read from memory address 23456H needs all three facts. The address lines identify 23456H. Control signals identify a memory read. The selected memory component then drives the requested bit pattern onto the data lines for the CPU to receive.
An address is a binary label. With independent address lines, there are possible bit combinations. The 8086 forms a 20-bit memory address, so it can select:
Its data path is 16 bits wide, so one properly aligned transfer can carry a 16-bit word. Address width and data width answer different questions: address width controls how many locations can be named; data width controls how many bits can move together.
The 8086 also distinguishes a memory address space from an I/O address space. The same low numeric address can exist in both spaces. A control signal such as M/IO tells external logic which space the current cycle targets.
Width changes capacity, transfer count, and hardware cost
A wider address bus selects more locations exponentially. Increasing from 16 to 20 address bits multiplies the location count by:
A wider data bus increases payload per transfer. An 8-bit bus moves one byte at a time, a 16-bit bus moves two, and a 32-bit bus moves four. A six-byte record therefore needs six, three, or two transfers respectively, assuming the system can use all available byte lanes.
Wider is therefore not automatically better. More signal lines require package pins, board traces, connectors, receivers, and often additional power. A designer chooses enough width to satisfy capacity and throughput constraints without paying for unused lanes.
Control lines do not carry the payload, but they make the address and data meaningful. Common minimum-mode 8086 controls include:
- M/IO to distinguish memory from I/O;
/RDand/WRto command a read or write;
- ALE to mark when a multiplexed address is valid;
- DT/R and
/DENto control external data transceivers; and
- READY to indicate whether the selected device can complete the transfer.
The leading slash means active low: /RD=0 asserts the read command, while /RD=1 leaves it inactive. Labels must include that convention because a low voltage is not the same thing as “nothing happening.”
A bus is a communication contract, not merely a bundle of copper. Correct bits sent at the wrong time, in the wrong direction, or to the wrong address space still form an incorrect transfer.
Section 9.1 has identified the information that must cross the interface. Section 9.2 arranges that information into T1 through T4 so a device knows when to capture an address, drive data, and report completion.