8.3 Control Unit and Micro-operations

Section 8.2 showed that the datapath contains many possible routes. The control unit turns one instruction into an ordered sequence of control decisions: which source to select, what the ALU should do, which storage element may change, and when a memory transfer may occur.

A micro-operation is one small state-changing action

A micro-operation is an elementary internal action such as copying one register to another, incrementing IP, reading memory, or asking the ALU to add. It is smaller than a machine instruction. One instruction usually requires several micro-operations.

Consider this teaching sequence for fetching an instruction byte:

• T0 — Address: copy the address formed from CS:IP to a memory-address latch.

• T1 — Read: assert the memory-read control and wait for the byte to arrive.

• T2 — Capture and advance: copy the returned byte into the instruction register and increment IP.

• T3 — Decode: interpret the captured opcode and choose the next control sequence.

The labels T0 through T3 name control time slots, not fixed real-world durations. A slow memory read can require wait states between request and capture. The address latch and instruction register are teaching-model internal registers; they are not additional programmer-visible 8086 registers.

Order follows data dependencies. A consumer cannot use a value before its producer makes that value available. Decode therefore cannot precede capture. IP may be incremented in the same slot as capture because the current fetch address has already been preserved in the address latch.

Parallel micro-operations are safe only when they do not compete for one resource and neither destroys an input the other still needs. Scheduling is a resource-and-dependency problem, not merely a matter of putting actions into adjacent boxes.

A control word activates compatible datapath signals

During one time slot, the control unit can issue a control word: a bundle of fields and enable bits that collectively describe the active datapath operation. A simple teaching control word might contain:

• source-A and source-B selector fields;

• an ALU-function field;

• a destination selector;

• RegisterWrite and FlagWrite enables; and

• MemoryRead and MemoryWrite enables.

For CX ← AX + BX, the word selects AX and BX, requests ADD, selects CX, and enables RegisterWrite. It does not need a memory command. For FLAGS ← test(AX), it can route AX through a pass operation and enable FlagWrite without changing a general register.

Some combinations are meaningless or dangerous. MemoryRead and MemoryWrite must not be asserted together for one ordinary bus transfer. RegisterWrite must be off when no valid destination data exists. FlagWrite must be on only when the instruction defines new flags.

Two broad controller organizations are common:

• Hardwired control derives signals from logic built around the opcode, current time slot, flags, and other conditions. It can be fast, but complex behavior is harder to modify.

• Microprogrammed control stores control words or encoded microinstructions in a control memory. It makes long sequences systematic, but fetching and decoding microinstructions adds design cost.

These are implementation strategies beneath the instruction set. A programmer sees the same architectural instruction behavior either way. Real processors can also combine techniques, so this teaching distinction is a design lens rather than a claim that every CPU belongs to only one category.

A wide, horizontal control word exposes many independent signals and can request more parallel work. A narrower, vertical encoding saves control-memory bits but needs extra decoding and may express less parallelism per microinstruction.

The control unit answers what happens in each slot. Section 8.4 adds physical delay and workload counts to answer how long the slots and complete programs take.