12.4 8259 Programmable Interrupt Controller

A single 8086 INTR pin cannot identify which of several devices requested service. The 8259 Programmable Interrupt Controller (PIC) collects eight request lines, applies masks and priority, raises one CPU request, and supplies an interrupt type during acknowledgement.

Follow a request through IRR, IMR, and ISR

Three 8-bit registers describe the controller’s essential state:

• The Interrupt Request Register (IRR) records pending IRQ0–IRQ7 requests.

• The Interrupt Mask Register (IMR) marks blocked sources; a 1 bit means masked.

• The In-Service Register (ISR) marks requests that have been acknowledged but not yet completed.

In fixed-priority mode, IRQ0 has the highest priority and IRQ7 the lowest. When an eligible request exists and the CPU accepts INTR, the 8086 produces interrupt-acknowledge (INTA) pulses. The 8259 moves the selected request from pending to in-service and supplies its interrupt type. At the end of the handler, an End of Interrupt (EOI) command clears the in-service state so lower-priority work can proceed.

Masking a pending request prevents selection but does not have to erase its IRR bit. Forgetting EOI leaves a request marked in service and can block requests of equal or lower priority. Sending EOI too early allows new service before the handler has made shared state safe.

Initialize vector mapping and cascade wiring

The 8259 is configured with Initialization Command Words (ICWs):

1. ICW1 begins initialization and describes basic operating form.

2. ICW2 supplies the interrupt-type base.

3. ICW3 describes master/slave cascade wiring when cascading is enabled.

4. ICW4 selects 8086/8088 processor mode and other service options.

The vector base must be aligned to eight types because the selected IRQ number supplies the low three bits. With base 20H, IRQ0–IRQ7 produce types 20H–27H. Each resulting type still indexes the IVT at four times the type number.

Two cascaded 8259s can expose 15 device request inputs: the slave contributes eight, but one master input is consumed by the cascade connection. On the master, ICW3 marks the IRQ line connected to a slave. On the slave, ICW3 gives that slave’s identity, which must equal the connected master IRQ number.

A configuration review checks ICW order, aligned non-overlapping vector ranges, cascade identity, 8086 mode, masks, and the handler’s EOI policy. A correct wiring diagram with an incorrect ICW3 still routes acknowledgement to the wrong place.

Chapter 12 replaced repeated status checking with event-driven control transfers, then traced vectors, stack frames, ISR discipline, nested priorities, and 8259 request routing. Chapter 13 uses these interrupt foundations with timers, data-transfer controllers, serial links, and sensor interfaces.